1. Field of the Invention
The present invention relates generally to digital logic circuitry, and more particularly, to a high-speed digital latch circuit using emitter-coupled logic circuitry and developing an output signal swing having a magnitude substantially proportional to temperature.
2. Description of the Prior Art
Digital-to-analog converter circuits are known in the art for converting a multiple bit digital input signal to a corresponding analog voltage. High speed digital-to-analog converter circuits fabricated upon monolithic substrates using bipolar transistor integrated circuit technology are widely available. However, such monolithic high speed digital-to-analog converters usually lack any means for storing the digital input signal to be processed by the converter. To avoid slowing the response time of the converter, such a storage means must necessarily have fast switching speeds. In addition, such a storage means must be relatively compact to avoid significant increases in the size of the monolithic substrate upon which the converter is fabricated and to avoid corresponding decreases in the production yields of such converters.
Since the digital input signal presented to such a converter is often generated by TTL-type logic circuitry, implementation of such a storage means using TTL circuitry would be an obvious alternative; in this manner the storage means would be input compatible with the source of the digital input signal. However, conventional TTL circuitry is typically slower than the bipolar converter circuitry and would therefore result in unacceptable signal delays. While techniques such as gold-doping of transistors and the use of Schottky diodes are known for increasing the speed of conventional TTL circuitry, such techniques are generally incompatible with the processing methods used to produce high-speed digital-to-analog converter circuits. Furthermore, the relatively large number of transistors needed to implement a TTL clocked data latch would significantly increase the size of the substrate upon which the converter is fabricated, particularly when the number of bits within the digital input signal, and hence the number of such latch circuits, is relatively large.
As an alternative to the use of TTL circuitry to form clocked data latches upon the converter substrate, relatively high-speed emitter-coupled logic structures, known to the art and employing series-gating techniques, might be used to form such clocked data latches. For example, emitter-function logic structures forming a gated latch and a clocked D-type flip-flop are illustrated in "Emitter Function Logic-Locig Family For LSI", by Skokan, IEEE Journal of Solid State Circuits, Vo. SC-8, No. 5, October, 1973, pages 356-361. A latch circuit and a master/slave flip-flop circuit utilizing current mode logic are illustrated in "High Speed Current Mode Logic For LSI", by Cooperman, IEEE Transactions on Circuits and Systems, Vol. CAS-27, No. 7, July, 1980, pages 626-635. Such emitter-coupled logic structures are generally compatible with the processing methods used to form high speed converter circuits and have sufficient switching speeds to avoid significant delays in the presentation of the digital input signal to the converter.
Typically, such emitter-coupled, series-gated latch circuits include an upper-level bias transistor having a base terminal coupled to a threshold or reference voltage and a collector terminal coupled by a load resistor to the positive-most power supply (usually ground potential). The bias transistor is emitter coupled to an input transistor having a base terminal which receives an input signal which switches between a high level of approximately ground voltage and a low level of approximately 0.8 volts below ground potential. The gate current and load resistor are typically selected to create a voltage swing of approximately 0.8 volts across the load resistance. The reference voltage is selected to be midway between the input signal swing, or approximately at 0.4 volts below ground potential. In order to latch the input data, a second emitter-coupled pair of transistors is provided. The second emitter-coupled transistor pair is often formed by fabricating the above-mentioned bias transistor as a double-emitter device and coupling the second such emitter to the emitter terminal of a feedback transistor. The base terminal of the feedback transistor is coupled to the collector of the bias transistor, and thus, the feedback portion of the latch is driven by a so-called single-ended feedback signal. A clocked, lower-level emitter-coupled gate switches gate current between the input and feedback emitter-coupled transistor pairs within the upper level of the gate structure for selectively switching the latch structure between an acquire mode and a latch mode for initially acquiring the data presented at the latch input and subsequently latching the same within the feedback stage, respectively.
Emitter-coupled latch circuits of the general type described above are subject to various limitations which somewhat restrict their performance. For example, the gate current within such series gated structures typically decreases with increasing temperature. Accordingly, the logic swing developed across the load resistor in such latch circuits decreases in magnitude with increasing temperatures. In contrast, the voltage differential which must necessarily be applied to the base terminals of an emitter coupled transistor pair to enture a given ratio between the current conducted by the on transistor and the current conducted by the off transistor actually increases with increasing temperatures. Consequently, such circuitry is typically designed so as to maintain at least a predetermined voltage swing at relatively high temperatures to assure a sufficient ratio of on current to off current at such temperatures. The result is that, at nominal temperatures, the voltage swing across the load resistor is actually much larger than is actually needed to maintain the same ratio of on current to off current within the emitter-coupled transistor pair. However, the relatively large swing at nominal temperatures results in the switching time of the latch being increased over that which could be obtained were a smaller voltage swing utilized.
Furthermore, the maximum temperature at which such circuitry may be operated without adversely affecting switching speed is limited by saturation of the base-collector junction of the bias transistor. When the bias transistor is turned on, the voltage at its collector may be 0.8 volts or more below ground potential, while its base is approximately 0.4 volts below ground. Consequently, the bias transistor base-collector junction is forward biased by 0.4 volts or more. When parasitic resistances within the transistor itself are accounted for, the actual forward bias across the base-collector junction of the transistor is even larger. At sufficiently high temperatures, the bias transistor begins operating in a saturated mode, thereby causing switching speed to slow down.
A further limitation of such prior art emitter-coupled latch circuits regards minimum edge speeds of clocking signals used to switch the latch circuit from the acquire mode to the latched mode. Depending upon the nature of the circuit and the edge speed of the clocking signal, a low voltage established at the collector of the bias transistor during the acquire mode may begin to rise toward ground potential before the lower level clock gate switches sufficient current to the feedback stage of the latch circuit to reestablish the low output level. In this case, the data acquired during the acquire mode may be lost before the latch circuit has completely switched to the latched mode of operation.
Yet another limitation of such prior art emitter-coupled latch circuits is the relative difficulty involved in interfacing the input portions of such circuits to other digital logic families, such as transistor-transistor logic (TTL). The threshold or reference voltage applied to the bias transistor within the upper level of such latch circuits is typically only 0.4 volts below the positive-most voltage supply. Such emitter-coupled circuits necessarily have difficulty responding to input signals of the type provided by TTL circuitry.
Similarly, it is often difficult to interface the output of such prior art latch circuits with the input portion of other types of digital logic because of the relatively small magnitude of the output signal swing as well as the need to reference the output signal relative to ground potential (or other positive supply voltage). For similar reasons, such emitter-coupled latch circuits are not well adapted to drive the input switching stages of high-speed digital-to-analog converters.
Finally, such prior art emitter-coupled latch structures have limited fan-out, i.e., the capability to drive other gates that are of the same type logic family. For example, the EFL type latch circuit described by Skokan requires an additional emitter diffusion within the output transistor for each additional gate to be driven thereby. The CML latch circuit disclosed by Cooperman has rather limited output drive capability unless the size of the load resistor is decreased which, in turn, increases the gate current and overall power consumed.
Accordingly, it is an object of the present invention to provide a clocked data latch circuit compatible with the fabrication methods and operating speeds of a high speed monolithic digital-to-analog converter and capable of being formed on the same substrate therewith as a relatively compact structure.
It is another object of the present invention to provide a high speed latch circuit utilizing emitter-coupled transistor switches wherein the magnitude of the nominal output voltage swing provided thereby is sufficiently large to maintain an adequate ratio of on-current to off-current within the feedback portion thereof without being so large as to unnecessarily increase the switching speed of the latch circuit.
It is a further object of the present invention to provide an emitter-coupled latch circuit wherein the magnitude of the output voltage swing increases proportionally with increased temperature for maintaining a predetermined ratio of on-current to off-current in similar circuits driven thereby despite changes in temperature.
It is still another object of the present invention to provide such an emitter-coupled latch circuit which may be operated at relatively high temperatures without adversely affecting the speed thereof.
It is yet another object of the present invention to provide such an emitter-coupled latch circuit wherein the tendency of the latch circuit to lose the state of the acquired data when being switched to the latched mode of operation is reduced.
It is a further object of the present invention to provide such an emitter-coupled latch circuit which is input capatible with TTL circuitry as well as other logic families.
It is a still further object of the present invention to provide such an emitter-coupled latch circuit which can provide an output signal having a voltage swing largely in excess of that used to retain the state of the data within the feedback stage of the latch circuit itself, to more easily drive other types of switching circuitry.
It is yet a further object of the present invention to provide such an emitter-coupled latch circuit wherein the fan-out capability of the latch circuit may be greatly increased with a minimum of extra components and power.
It is yet another object of the present invention to provide a bias circuit for such an emitter-coupled latch circuit wherein the threshold level, or reference voltage, tracks with the output signal swing over changes in temperature so as to remain substantially centered within the output voltage swing.
These and other objects of the present invention will become more apparent to those skilled in the art as the description thereof proceeds.